CLA40MT1200NPB 1~ triac three quadrants operation: qi - qiii high efficiency thyristor 4 1 3 part number CLA40MT1200NPB backside: anode/cathode - negative half cycle positive half cycle + qii qi qiii qiv i gt - + i gt three q u a dr a nt s o p e r a tion note: all polarities are referenced to t1 t2 t1 ref (-) i gt t2 t1 ref (-) i gt t2 t1 ref (+) i gt tav t v v 1.37 rrm 20 1200 = v = v i = a features / advantages: applications: package: triac for line frequency three quadrants operation - qi - qiii planar passivated chip long-term stability of blocking currents and voltages line rectifying 50/60 hz softstart ac motor control dc motor control power converter ac power control lighting and temperature control to-220 industry standard outline rohs compliant epoxy meets ul 94v-0 high creepage distance between terminals the data contained in this product data sheet is ex clusively intended for technically trained staff. t he user will have to evaluate the suitability of th e product for the intended application and the completeness of the product data with respect t o his application. the specifications of our compon ents may not be considered as an assurance of compo nent characteristics. the information in the valid application- and assembly notes must be considered. should you require produc t information in excess of the data given in this p roduct data sheet or which concerns the specific application of your product, please co ntact the sales office, which is responsible for yo u. due to technical requirements our product may conta in dangerous substances. for information on the typ es in question please contact the sales office, whi ch is responsible for you. should you intend to use the product in aviation, i n health or live endangering or life support applic ations, please notify. for any such application we urgently recommend - to perform joint risk and quality assessments; - the conclusion of quality agreements; - to establish joint measures of an ongoing product survey, and that we may make delivery dependent on the realization of any such measures. terms conditions of usage: ixys reserves the right to change limits, condition s and dimensions. 20150827b data according to iec 60747and per semiconductor un less otherwise specified ? 2015 ixys all rights reserved
CLA40MT1200NPB v = v a2s a2s a2s a2s symbol definition ratings typ. max. i v i a v t 1.37 r 0.8 k/w min. 20 v v 10 t = 25c vj t = c vj ma 1.5 v = v t = 25c vj i = a t v t = c c 115 p tot 155 w t = 25c c 20 1200 forward voltage drop total power dissipation conditions unit 1.71 t = 25c vj 125 v t0 v 0.89 t = c vj 150 r t 24 m ? v 1.37 t = c vj i = a t v 20 1.83 i = a40 i = a40 threshold voltage slope resistance for power loss calculation only a 125 v v 1200 t = 25c vj i a 44 p gm w t = 30 s 5 max. gate power dissipation p t = c c 150 w t = 1 p p gav w 0.2 average gate power dissipation c j 12 junction capacitance v = v400 t = 25c f = 1 mhz r vj pf i tsm t = 10 ms; (50 hz), sine t = 45c vj max. forward surge current t = c vj 150 i2t t = 45c value for fusing t = c 150 v = 0 v r v = 0 v r v = 0 v v = 0 v t = 8,3 ms; (60 hz), sine t = 10 ms; (50 hz), sine t = 8,3 ms; (60 hz), sine t = 10 ms; (50 hz), sine t = 8,3 ms; (60 hz), sine t = 10 ms; (50 hz), sine t = 8,3 ms; (60 hz), sine vj r vj r thjc thermal resistance junction to case t = c vj 150 200 215 145 140 aa a a 170 185 200 190 1200 300 s rms forward current per phase rms tav 180 sine average forward current (di/dt) cr a/s 150 repetitive, i = t vj = 150 c; f = 50 hz critical rate of rise of current v gt gate trigger voltage v = 6 v t = c25 (dv/dt) t = 150c critical rate of rise of voltage a/s 500 v/s t = s; i a; v = ? v r = ; method 1 (linear voltage rise) vj d vj 60 a t pg = 0.3 di /dt a/s; g = 0.3 drm cr v = ? v drm gk 500 1.3 v t = c -40 vj i gt gate trigger current v = 6 v t = c25 d vj 40 ma t = c -40 vj 1.6 v 60 ma v gd gate non-trigger voltage t = c vj 0.2 v i gd gate non-trigger current 1 ma v = ? v d drm 150 latching current t = c vj 70 ma i l 25 t s p = 10 i a; g = 0.3 di /dt a/s g = 0.3 holding current t = c vj 50 ma i h 25 v = 6 v d r = gk gate controlled delay time t = c vj 2 s t gd 25 i a; g = 0.3 di /dt a/s g = 0.3 v = ? v d drm turn-off time t = c vj 150 s t q di/dt = a/s 10 dv/dt = v/s 20 v = r 100 v; i a; t = 20 v = ? v drm t s p = 200 non-repet., i = 20 a t 125 r thch thermal resistance case to heatsink k/w rectifier 1300 rrm/drm rsm/dsm max. non-repetitive reverse/forward blocking voltag e max. repetitive reverse/forward blocking voltage r/d reverse current, drain current tt r/d r/d 200 0.50 ixys reserves the right to change limits, condition s and dimensions. 20150827b data according to iec 60747and per semiconductor un less otherwise specified ? 2015 ixys all rights reserved
CLA40MT1200NPB ratings xxxxxx zyyww logo part number date code lot # abcdef product marking assembly line c l a 40 mt 1200 n pb part description thyristor (scr) high efficiency thyristor (up to 1200v) 1~ triac three quadrants operation: qi - qiii to-220ab (3) = = = = current rating [a] reverse voltage [v] = = = = package t op c m d nm 0.6 mounting torque 0.4 t vj c 150 virtual junction temperature -40 weight g 2 symbol definition typ. max. min. conditions operation temperature unit f c n 60 mounting force with clip 20 i rms rms current 35 a per terminal 125 -40 to-220 similar part package voltage class cla40mt1200npz to-263ab (d2pak) (2hv) 1200 delivery mode quantity code no. ordering number marking on product ordering CLA40MT1200NPB 517038 tube 50 CLA40MT1200NPB standard t stg c 150 storage temperature -40 threshold voltage v 0.89 m ? v 0 max r 0 max slope resistance * 21 equivalent circuits for simulation t = vj i v 0 r 0 thyristor 150 c * on die level ixys reserves the right to change limits, condition s and dimensions. 20150827b data according to iec 60747and per semiconductor un less otherwise specified ? 2015 ixys all rights reserved
CLA40MT1200NPB dim. millimeter inches min. max. min. max. a 4.32 4.82 0.170 0.190 a1 1.14 1.39 0.045 0.055 a2 2.29 2.79 0.090 0.110 b 0.64 1.01 0.025 0.040 b2 1.15 1.65 0.045 0.065 c 0.35 0.56 0.014 0.022 d 14.73 16.00 0.580 0.630 e 9.91 10.66 0.390 0.420 e 2.54 bsc 0.100 bsc h1 5.85 6.85 0.230 0.270 l 12.70 13.97 0.500 0.550 l1 2.79 5.84 0.110 0.230 ?p 3.54 4.08 0.139 0.161 q 2.54 3.18 0.100 0.125 3x b2 e ?p q d l1 l 3x b 2x e c a2 h1 a1 a = supplier option 1 2 3 4 4 1 3 outlines to-220 ixys reserves the right to change limits, condition s and dimensions. 20150827b data according to iec 60747and per semiconductor un less otherwise specified ? 2015 ixys all rights reserved
CLA40MT1200NPB 0,01 0,1 1 60 80 100 120 140 1 6 0 0,5 1,0 1,5 2,0 2,5 0 10 20 30 40 10 0 10 1 10 2 10 3 10 4 0,0 0,2 0,4 0,6 0,8 1,0 i tsm [a] i t [ a] v t [v] t [ms] z thjc [k/w] 2 3 4 5 6 7 8 9 01 1 10 100 1 0 00 i 2 t [a 2 s] t [ms] i t(av)m [a] t c [c] 0 25 50 75 100 125 150 175 0 10 20 30 40 fig. 1 forward characteristics fig. 3 i 2 t versus time (1-10 ms) t [s] fig. 6 max. forward current at case temperature fig. 2 surge overload current fig. 8 transient thermal impedance t vj = 25c t vj = 125c t vj = 45c 50 hz, 80% v rrm t vj = 125c t vj = 45c v r = 0 v 0 10 20 0 10 20 30 40 i t(av) [a] p (av) [w] fig. 7a power dissipation versus direct output current fig. 7b and ambient temperature 0 50 100 150 t amb [c] dc = 1 0.5 0.4 0.33 0.17 0.08 10 100 1000 1 10 100 1000 i g [ma] v g [v] t gd [s] i g [ma] typ. limit t vj = 125c fig. 4 gate trigger characteristics fig. 5 gate controlled delay time dc = 1 0.5 0.4 0.33 0.17 0.08 t vj = 125c t vj = 150c r thi [k/w] t i [s] 0.10 0.0100 0.08 0.0011 0.20 0.0250 0.21 0.3200 0.21 0.0900 r thha 0.4 0.6 0.8 1.0 2.0 4.0 0 25 50 75 0 1 2 3 4 i gd : t vj = 125c i gd : t vj = 25c i gd : t vj = 25c i gd : t vj = 0c i gd : t vj = -40c a b b b c thyristor ixys reserves the right to change limits, condition s and dimensions. 20150827b data according to iec 60747and per semiconductor un less otherwise specified ? 2015 ixys all rights reserved
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